Intel is developing a programmable processor with many cores that is compatible with the x86 instruction set and capable of performing 1 trillion floating-point operations per second, a senior company executive said Tuesday at the Intel Developer Forum in Beijing.
Called Larabee, the upcoming chip will offer an array of processor cores in a parallel architecture and will be demonstrated next year. "High-throughput, parallel machine architecture is something we see as critical," said Pat Gelsinger, senior vice president and general manager of Intel's Digital Enterprise Group.
The introduction of Larabee follows on the heels of the demonstration earlier this year of Intel's Terascale chip, which included 80 processor cores and was shown processing 2 trillion floating-point operations per second at IDF. While an impressive engineering achievement, the Terascale chip is not compatible with the x86 instruction set, which lies at the heart of all Intel processors and has no future as a commercial product in its current form.
That's where Larabee comes in. When released, the chip will be aimed at high-performance computing applications, such as scientific research and financial services. "We'll be able to demonstrate it in 2008," Gelsinger said. He did not offer a detailed look at the chip's specifications.
Gelsinger also used his keynote to announce Tolapai, a chip that combines an x86 processor core with an integrated chipset and encryption co-processor, set to enter production later this year. Integrating these functions results in a chip that offers faster throughput, consumes less power and takes up less space, he said.
The Tolapai chip is designed for dedicated servers and appliances that handle tasks such as virus scanning and encryption. A similar chip that integrates an x86 processor core with other components for consumer-electronics applications is slated for release next year, said Eric Kim, senior vice president and general manager of Intel's Digital Home Group.
These chips are just the beginning of Intel's plans for integration. "You can expect to see us do a wider range of system-on-chip solutions," Gelsinger said.
One possible area where such a chip would be useful is the mobile space due to the lower power consumption and the smaller package size offered by a system-on-chip. "Power, integration, form factor are all very critical for these kinds of devices," Gelsinger said.