Intel has shed a little more light on its forthcoming dual-core mobile chip Thursday in a briefing with reporters, confirming that the Yonah processor's two cores will share a single bank of cache memory.
Yonah is the dual-core version of Intel's Pentium M processor for notebooks and miniature desktops, scheduled for release in the first quarter of next year. Unlike Intel's first dual-core designs for desktop PCs, Yonah is a much more integrated design that shares storage and power management resources within the chip, said Mooly Eden, vice president and general manager of Intel's mobile platforms group.
The just-released dual-core Pentium D processor uses separate 1MB cache memory banks dedicated to each core. In the Yonah processor, a single 2MB cache memory bank is available to both cores, reducing the chance that data will have to leave the chip to be temporarily stored in a system's main memory bank, Eden said.
Cache memory is used to store frequently accessed bits of data in a repository close to the CPU. Data stored in cache memory can be accessed much faster than data stored in a PC's memory, because the CPU doesn't have to exit the processor to find that data.
In Yonah, each processor core has access to the full 2MB of cache. This means that one core can store a piece of data in the cache that might be needed later by the other core, and the other core can access that data without having to leave the chip, Eden said. The larger amount of storage allows Yonah's cores to spend less time navigating through Intel's front-side bus and more time executing instructions, which will dramatically improve performance, he said.
The shared cache design also allows Intel to eliminate some of the disadvantages of its front-side bus design, which many analysts see as a bottleneck in the dual-core era. The front-side bus is the connection between the processor and the memory bank via a chipset. On Intel's chips, this interface is located on the chipset, farther away from the CPU. But on rival AMD's chips, the memory controller is on the same chip as the CPU, where it can access data from the memory much faster than can a front-side bus.
Intel plans eventually to move to a similar design, but in the meantime it has been raising the speed at which its buses move data in order to cope with the increased activity of two processor cores. Yonah's two cores will share a single front-side bus running at 667MHz, an improvement in frequency over the 533MHz bus used by the current generation of Pentium M processors, Eden said.
Yonah will also use sophisticated power management techniques to make sure that each core is only drawing as much power as it needs to process its instructions, Eden said. The processor can monitor the application activity passing through each core and allocate power as needed between the cores, reducing power consumption during idle moments, he said.
As a result, the battery life of notebooks with the Yonah and the rest of the Napa platform should exceed that of the current generation of Intel's Centrino technology, Eden said. Napa is the code name for the combination of Yonah, a new mobile chipset, and a new wireless chip that makes up the Centrino brand.
Intel plans to aggressively introduce dual-core processors over the next year. The company was forced to accelerate its dual-core processors after realizing that it could no longer wring any more performance out of single-core Pentium 4 chips without melting motherboards. Processor analysts and chip enthusiasts have turned their noses up at Intel's initial Pentium D design, labeling it inelegant compared to AMD's dual-core chips.
The difference between the dual-core Pentium D processor and Yonah is also quite stark, Eden said in response to a reporter's question.
"You are asking me what is the difference between a microprocessor and a donkey," he said.